This disclosure relates generally to semiconductor integrated circuits and, more particularly, to techniques for controlling access of multiple scan devices to a scan chain.
Scan chains may be employed in integrated circuits (chips) to facilitate design for test. Scan chains provide a relatively simple way to set and observe latches or flip-flops in the chip. The basic structure of a scan includes providing scan_in and scan_out signals to define the input and output of a scan chain. In a full scan mode each input (scan_in) usually only drives only one scan chain and an output (scan_out) of each scan chain is observed. In a chip that does not have a full scan design, i.e., a chip that has sequential circuits such as memory elements that are not part of the scan chain, sequential pattern generation may be employed. Test pattern generation for sequential circuits searches for a sequence of vectors to detect a particular fault through the space of all possible vector sequences.
Modern integrated circuits design has greatly advanced and layouts of current integrated circuits are often highly complex. In general, integrated circuits may need to be initialized to a defined state. Moreover, functional tests of integrated circuits components, e.g., a scan chain of latches, may be complicated and need to be performed in a reliable manner. In general, conventional approaches have exclusively assigned a scan chain to one scan device.